Integrated circuits (ICs) formed on semiconductor substrates include multiple active and passive components, such as resistors, inductors, capacitors, transistors, amplifiers, etc. Such components are fabricated to a design specification that defines the ideal physical/electrical characteristics the component will exhibit (e.g., resistance, inductance, capacitance, gain, etc.). Though it is desirable to verify that each component fabricated complies with its specific design specification, typically, after integration into a circuit, an individual component cannot be readily tested. Thus, “stand-alone” copies of the individual IC components, components fabricated with the same process and with the same physical/electrical characteristics as the IC components, are fabricated on the wafer; and it is assumed that the physical/electrical properties measured for the “stand-alone” copies represent those of the non-tested individual IC components.
During testing, the “stand-alone” copy, referred to as the “device-under-test” (DUT), is electrically connected to leads and test pads, which are further connected to external testing equipment. Though the physical/electrical properties measured should accurately represent those of the DUT (and the individual IC component represented), the test pads and leads contribute physical/electrical characteristics, known as “parasitics” (e.g., resistance, capacitance, and inductance from the test pads and leads), that contribute to the measured characteristics of the DUT. The parasitics are factored out or extracted by a process known as “de-embedding” to reveal the intrinsic characteristics of the DUT alone.
Thus, accurate de-embedding methods are required to eliminate the parasitic contributions and accurately describe the intrinsic characteristics of the DUT (and ultimately, the individual IC component represented). Currently, on-wafer de-embedding methods referred to as “open-short,” “open-thru,” and “thru-reflect-line” (“TRL”) have been widely used to subtract parasitics such as resistance, inductance, and capacitance arising from the test pads and leads at high frequencies (up to the GHz level). However, each of these methods presents problems: (1) the open-short method results in over de-embedding of the inductance parasitics from the lead metal lines; (2) the open-thru method accuracy depends on model fitting quality, often resulting in inaccurate parasitics extracted; (3) the TRL method requires at least three DUTs to cover a wide frequency range; and (4) all current methods use an approximate open pad. Furthermore, current metal routings have simply included a metal layer over a substrate, causing increased parasitic capacitance and lower characteristic impedance issues.
Accordingly, what is needed is a test structure and method for improving the accuracy of de-embedding parasitics.